The present invention relates to an integrated circuit, and more particularly to an integrated circuit which is protected from noise by a chip capacitor mounted on its package.
As the packing density of the elements of integrated circuit devices (ICs) increases, it is becoming increasingly important to protect the ICs from noise in order to secure reliable operation. Because circuit design becomes more critical with higher degrees of integration, and the margins between the lower or higher level of digital signals and the threshold levels are reduced, highly integrated circuitry is subject to malfunction due to noise. In order to reduce this problem a bypass capacitor can be connected between the power source and the ground.
Usually such a capacitor is mounted on the printed circuit board and the leads of the capacitor are connected to the power supply line and the ground line respectively. The capacitor protects the IC from noise induced on the power supply line. As integration density and speed increase, however, it becomes impossible to ignore the distributed inductance between the capacitor and the IC. It is often reported that the pulses generated by the IC itself have been induced on the power source line, and that this noise is not smoothed out by the bypass capacitor but is instead superposed on the source voltage, thus causing malfunctions.
Recently a couple of approaches have been tried in order to overcome this problem. One of these approaches was to mount a capacitor on the top of an IC package and to wire the capacitor's leads to the ground and power source pins of the IC. However this approach did not reduce the wire length enough to effectively eliminate the inductance, and so the operation of the IC remained insufficient.
Another approach to a solution was to mount a capacitor in the IC package. A chip capacitor was placed on the die or chip bonding area of the package and the IC die or chip was mounted on the chip capacitor. This arrangement resulted in other problems. A very clean environment is needed for the IC die, and placing the capacitor in the same chamber with the IC die tended to contaminate the environment. Heat problems were also troublesome, since the heat generated by the IC should be released from the package, but the thermal resistance was increased by stacking the IC die on the chip capacitor. Another problem was that the package needed to be redesigned since the chamber for the IC die needed to be higher in order to also accommodate the chip capacitor. This increases the cost of the package.